STM32F103CBU6 datasheet(14/105 Pages) STMICROELECTRONICS

14 / 105 page

Description

STM32F103x8, STM32F103xB

14/105

DocID13587 Rev 16

2.3

Overview

2.3.1

ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

The STM32F103xx performance line family having an embedded ARM core, is therefore

compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2

Embedded Flash memory

64 or 128 Kbytes of embedded Flash is available for storing programs and data.

2.3.3

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

2.3.4

Embedded SRAM

Twenty Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states.

2.3.5

Nested vectored interrupt controller (NVIC)

The STM32F103xx performance line embeds a nested vectored interrupt controller able to

handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of

Cortex™-M3) and 16 priority levels.



Closely coupled NVIC gives low-latency interrupt processing



Interrupt entry vector table address passed directly to the core



Closely coupled NVIC core interface



Allows early processing of interrupts



Processing of late arriving higher priority interrupts



Support for tail-chaining



Processor state automatically saved



Interrupt entry restored on interrupt exit with no instruction overhead

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