STM32F217VG datasheet(154/173 Pages) STMICROELECTRONICS

154 / 173 page

Application block diagrams

STM32F21xxx

154/173

Doc ID 17050 Rev 8

A.2

Application example with regulator OFF

Figure 82.

Regulator OFF/internal reset ON

This mode is available only on UFBGA176.

In regulator bypass mode, PA0 is used as power-on reset. The connection between PA0 and NRST can consequently

prevent debug connection. If the debug connection under reset or pre-reset is required, the user must manage the reset

and the power-on reset separately.

A.3

USB OTG full speed (FS) interface solutions

Figure 83.

USB OTG FS (full speed) device-only connection

The same application can be developed using the OTG HS in FS mode to achieve enhanced performance

thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.

REGOFF

VCAP_1

ai18476

VCAP_2

PA0

NRST

Application reset signal

(optional)

1.2 V

VDD

(1.8 to 3.6 V)

Power-down reset risen

after VCAP_1/VCAP_2 stabilization

REGOFF

VCAP_1

VCAP_2

PA0

1.2 V

VDD

(1.8 to 3.6 V)

Power-down reset risen

before VCAP_1/VCAP_2 stabilization

NRST

IRROFF

VDD

Application reset

signal (optional)

VCAP_1/2 monitoring

Ext. reset controller active

when VCAP_1/2 < 1.08 V

STM32F20xxx

5V to VDD

Volatge regulator (1)

VDD

VBUS

VSS

PA9

PA12

PA11

OSC_IN

OSC_OUT

ai17295

STM32F217VG 数据表(PDF) 154 Page - STMicroelectronics

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