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STM32F217VG 数据表(PDF) 73 Page - STMicroelectronics |
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STM32F217VG 数据表(HTML) 73 Page - STMicroelectronics |
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73 / 173 page  STM32F21xxx Electrical characteristics Doc ID 17050 Rev 8 73/173 Table 19. Typical and maximum current consumption in Sleep mode Symbol Parameter Conditions fHCLK Typ Max(1) Unit TA = 25 °C TA = 85 °C TA = 105 °C IDD Supply current in Sleep mode External clock(2), all peripherals enabled(3) 120 MHz 38 51 61 mA 90 MHz 30 43 53 60 MHz 20 33 43 30 MHz 11 25 35 25 MHz 8 21 31 16 MHz 6 19 29 8 MHz 3.6 17.0 27.0 4 MHz 2.4 15.4 25.3 2 MHz 1.9 14.9 24.7 External clock(2), all peripherals disabled 120 MHz 8 21 31 90 MHz 7 20 30 60 MHz 5 18 28 30 MHz 3.5 16.0 26.0 25 MHz 2.5 16.0 25.0 16 MHz 2.1 15.1 25.0 8 MHz 1.7 15.0 25.0 4 MHz 1.5 14.6 24.6 2 MHz 1.4 14.2 24.3 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). |
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