STM32F217VG datasheet(107/173 Pages) STMICROELECTRONICS

107 / 173 page

STM32F21xxx

Electrical characteristics

Doc ID 17050 Rev 8

107/173

Table 52.

I2S characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fCK

1/tc(CK)

I2S clock frequency

Master, 16-bit data,

audio frequency = 48 kHz, main

clock disabled

1.23

1.24

MHz

Slave

64FS

(1)

tr(CK)

tf(CK)

I2S clock rise and fall time

capacitive load CL = 50 pF

(2)

tv(WS)

(3)

WS valid time

Master

0.3

th(WS)

(3)

WS hold time

Master

tsu(WS)

(3)

WS setup time

Slave

th(WS)

(3)

WS hold time

Slave

tw(CKH)

(3)

tw(CKL)

(3)

CK high and low time

Master fPCLK= 30 MHz

396

tsu(SD_MR)

(3)

tsu(SD_SR)

(3)

Data input setup time

Master receiver

Slave receiver

th(SD_MR)

(3)(4)

th(SD_SR)

(3)(4)

Data input hold time

Master receiver: fPCLK= 30 MHz,

Slave receiver: fPCLK= 30 MHz

tv(SD_ST)

(3)(4)

Data output valid time

Slave transmitter (after enable

edge)

th(SD_ST)

(3)

Data output hold time

Slave transmitter (after enable

edge)

tv(SD_MT)

(3)(4)

Data output valid time

Master transmitter (after enable

edge)

th(SD_MT)

(3)

Data output hold time

Master transmitter (after enable

edge)

FS is the sampling frequency. Refer to the I2S section of the STM32F20xxx/21xxx reference manual for more details. fCK

values reflect only the digital peripheral behavior which leads to a minimum of (I2SDIV/(2*I2SDIV+ODD), a maximum of

(I2SDIV+ODD)/(2*I2SDIV+ODD) and FS maximum values for each mode/condition.

Refer to Table 45: I/O AC characteristics.

Based on design simulation and/or characterization results, not tested in production.

Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.

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