STM32F415VG datasheet(111/186 Pages) STMICROELECTRONICS

111 / 186 page

DocID022063 Rev 4

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STM32F415xx, STM32F417xx

Electrical characteristics

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters.

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to

±8 mA, and sink or

source up to

±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can

sink or source up to

±3mA. When using the PC13 to PC15 GPIOs in output mode, the

speed should not exceed 2 MHz with a maximum load of 30 pF.

Table 47. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

TTL ports

2.7 V ≤ VDD ≤ 3.6 V

0.8

VIH(1) Input high level voltage

2.0

VIL

Input low level voltage

CMOS ports

1.8 V ≤ VDD ≤ 3.6 V

0.3VDD

VIH(1) Input high level voltage

0.7VDD

Vhys

I/O Schmitt trigger voltage hysteresis(2)

-200

IO FT Schmitt trigger voltage

hysteresis(2)

5% VDD(3)

Ilkg

I/O input leakage current (4)

VSS ≤ VIN ≤ VDD

±1

µA

I/O FT input leakage current (4)

VIN = 5V

RPU

Weak pull-up equivalent

resistor(5)

All pins

except for

PA10 and

PB12

VIN = VSS

PA10 and

PB12

811

RPD

Weak pull-down

equivalent resistor

All pins

except for

PA10 and

PB12

VIN = VDD

PA10 and

PB12

811

CIO(6) I/O pin capacitance

1. Tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order)

6. Guaranteed by design, not tested in production.

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