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STM32F415VG 数据表(PDF) 119 Page - STMicroelectronics |
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STM32F415VG 数据表(HTML) 119 Page - STMicroelectronics |
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119 / 186 page ![]() DocID022063 Rev 4 119/186 STM32F415xx, STM32F417xx Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14 with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 54. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V)(1)(2) 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. fSCL (kHz) I2C_CCR value RP = 4.7 kΩ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE Table 55. SPI dynamic characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SPI clock frequency Master mode, SPI1, 2.7V < VDD < 3.6V -- 42 MHz Slave mode, SPI1, 2.7V < VDD < 3.6V 42 1/tc(SCK) Master mode, SPI1/2/3, 1.7V < VDD < 3.6V -- 21 Slave mode, SPI1/2/3, 1.7V < VDD < 3.6V 21 Duty(SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 % |
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