STM32F415VG datasheet(145/186 Pages) STMICROELECTRONICS

145 / 186 page

DocID022063 Rev 4

145/186

STM32F415xx, STM32F417xx

Electrical characteristics

Figure 60. Synchronous multiplexed PSRAM write timings

th(CLKH-ADV)

FSMC_A/D[15:0] valid data after FSMC_CLK high

tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high

th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high

1. CL = 30 pF.

2. Based on characterization, not tested in production.

Table 80. Synchronous multiplexed PSRAM write timings(1)(2)

Symbol

Parameter

Min

Max

Unit

tw(CLK)

FSMC_CLK period

2THCLK

-ns

td(CLKL-NExL)

FSMC_CLK low to FSMC_NEx low (x=0..2)

td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low

td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high

td(CLKL-AV)

FSMC_CLK low to FSMC_Ax valid (x=16…25)

Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued)

FSMC_CLK

FSMC_NEx

FSMC_NADV

FSMC_A[25:16]

FSMC_NWE

FSMC_AD[15:0]

AD[15:0]

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

tw(CLK)

Data latency = 0

BUSTURN = 0

td(CLKL-NExL)

td(CLKL-NExH)

td(CLKL-NADVL)

td(CLKL-AV)

td(CLKL-NADVH)

td(CLKL-AIV)

td(CLKL-NWEH)

td(CLKL-NWEL)

td(CLKL-NBLH)

td(CLKL-ADV)

td(CLKL-ADIV)

td(CLKL-Data)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

ai14992g

td(CLKL-Data)

FSMC_NBL

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