AS8515 datasheet(45/65 Pages) AMSCO

45 / 65 page

www.ams.com

Revision 0.7

45 - 65

AS8515

Datasheet - 4-W i re SPI Interf ace

9.1.1 SPI Frame

A frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an integer number of

bytes. Command is coded on the 1 first bit, while address is given on LSB 5 bits (see Table 48).

If the command is read or write, one or more bytes follow. When the micro-controller sends more bytes (keeping CS LOW and SCLK toggling),

the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses.

9.1.2 Write Command

For Write command C0 = 0.

After the command code C0 and two reserved bits, the address of register to be written has to be provided from the MSB to the LSB. Then one

or more data bytes can be transferred, always from the MSB to the LSB. For each data byte following the first one, used address is the

incremented value of the previously written address. Each bit of the frame has to be driven by the SPI master on the SPI clock transfer edge and

the SPI slave on the next SPI clock edge samples it. These edges are selected as per clock polarity settings. In the following figures two

examples of write command (without and with address self-increment.

Figure 27. Protocol for Serial Data Write with Length = 1

Table 48. Command Bits

Command Bits

Reserved

Command

<A4:A0>

Description

WRITE

ADDRESS

Writes data byte on the given starting address

READ

ADDRESS

Reads data byte from the given starting address

SCLK

SDI

SDO

RES1 RES0

Transfer edge

Sampling edge

Data D7 – D0 is moved to

Address A4..A0 here

AS8515 数据表(PDF) 45 Page - ams AG

AS8515 数据表(HTML) 45 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

数据表下载