AS8515 datasheet(53/65 Pages) AMSCO

53 / 65 page

www.ams.com

Revision 0.7

53 - 65

AS8515

Datasheet - 4-Wi re SP I Interf ace

Digital Control Registers

CLK_REG

(Clock Control Register)

0010_0000

R/W

D[7:6]

Oversampling frequency clock selection. Default is 00

(high speed (HS) internal Clock)

Internal HS Clock with No Clock Output

Internal HS Clock with Clock Output

External Clock

D[5:4]

These two bits select the division ratio for HS clock/

external clock. Default is 10 (division by 4)

No division

Divide by 2

Divide by 4

Divide by 8

D[3:2]

These two bits select the division ratio of HS clock, by

which it should be divided before providing it on CLK

pin. Default is 00 (No Division)

No Division

Divide by 2

Divide by 4

Divide by 8

D[1]

This bit selects the division ratio of LS clock

LS _CLK undivided (Low Speed clock)

LS _CLK divide by 2

D[0]

Reserved

RESET_REG

(Reset Control Register)

1100_0000

R/W

D[7]

Entire device can be soft reset by writing “0” into this

out of Reset

D[6]

Measurement Path can be soft reset by writing “0” into

this register bit. This bit will take a default 1 value after

Measurement Path is reset.

D[5:0]

Reserved

Table 49. Control Registers

Addr in

HEX

POR Value

R/W

8-bit Control / Status Data

AS8515 数据表(PDF) 53 Page - ams AG

AS8515 数据表(HTML) 53 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

数据表下载