MB86604LPFV datasheet(5/56 Pages) FUJITSU

5 / 56 page

MB86604L

Note: The SCSI interface input/output pins can be connected to a single-end type SCSI bus.

MPU Interface

(Continued)

Phase name

MSG

C/D

I/O

Transfer direction

Initiator

Target

Data-out phase

→

Data-in phase

←

Command phase

→

Status phase

←

Message-out phase

→

Message-in phase

←

number

Symbol*

Pin name

I/O

Function

CS0

Chip select 0

This is a chip select 0 pin used by MPU to select the SPC as an

I/O device. This is an active-low pin.

CS1

Chip select 1

This is a chip select 1 pin to select when MPU inputs/outputs the

data on DMA bus through SPC. This is an active-low pin.

98, 97, 96,

95, 94, 93,

92, 91

D15

Data 15

data 8

I/O

These pins are for the upper byte and parity bit of MPU data bus.

When the CS0 input is valid, these pins serve as I/O ports for the

SPC internal registers. When the CS1 input is valid, these pins

serve as I/O ports for the DMA bus data.

UDP

Upper data

parity

89, 88, 87,

86, 85, 84,

83, 82

Data 7

data 0

I/O

These pins are for the lower byte and parity bit of the MPU data

bus. When the CS0 input is valid, these pins serve as I/O ports

for the SPC internal registers. When the CS1 input is valid, these

pins serve as I/O ports for the DMA bus data.

LDP

Lower data

parity

76, 75, 74,

73, 72

Address 4

address 0

These are address input pins to select the SPC internal

registers.

2RD

(R/W)

Read

(read/write)

In the 80-series mode, this is a read signal input pin (IORD or

RD) that MPU reads the SPC. This read signal pin is an active-

low. In the 68-series mode, this pin functions as the control

signal input (R/W) to control the read/write operation to the SPC.

In the read operation, this pin is an active-high. In the write

operation, this pin is an active-low.

1WR

(LDS)

Write

(lower data

strobe)

In the 80-series mode, this pin is a write signal input pin (IOWR

or WR) that MPU writes to the SPC. This write signal input pin is

active-low. In the 68-series mode, this pin function as the lower

data strobe signal input (LDS) that MPU outputs when the lower

byte of data bus is valid. The LDS pin is an active-low.

MB86604LPFV 数据表(PDF) 5 Page - fujitsu semiconductor

MB86604LPFV 数据表(HTML) 5 Page - fujitsu semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载