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MB86604LPFV 数据表(PDF) 38 Page - fujitsu semiconductor |
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MB86604LPFV 数据表(HTML) 38 Page - fujitsu semiconductor |
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38 / 56 page ![]() 38 MB86604L (b) Output timing (target → initiator) *1: The position number indicates the position in the waveform. *2: “S” value is based on the asychronous set up time setting register (address 17h). Note: The output timing definitions are not applied when the data register is EMPTY in the data phase. Parameter Symbol Value Unit Base signal Position*1 Min. Max. ACK “L” assert time REQ “L” tRQAKL A0 — ns REQ “H” negate time ACK “L” tAKRQH B— 60 ns ACK “H” negate time REQ “H” tRQAKH C0 — ns Time from output data valid to REQ “L” assert *2 —tDBRQ D S • tCLK – 10 —ns Output data hold time ACK “L” thDB E2 tCLK —ns REQ “L” assert time ACK “H” tAKRQ1 F— 40 ns A Valid data E REQ ACK F C D B D * Valid data DB7 to DB0 DBP ! *+, 34567 ?@A t AKRQ2 t AKRQ1 t RQAKH t RQAKL t hDB t DBRQ t DBRQ t AKRQH *: The ACK “L” → REQ “L” time (tAKRQ2) is defined by either longer of (tAKRQH + tRQAKH + tAKRQ1) or (thDB + tDBRQ). |
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