MSP430F5259 datasheet(3/107 Pages) TI1

3 / 107 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

www.ti.com

SLAS903A – MAY 2013 – REVISED JULY 2013

Table 1. Family Members(1)(2)

USCI

Channel

ADC10_

Comp_

Flash

SRAM

I/O

Package

Device

Timer_A(3)

Timer_B(4)

BSL Type

(KB)

DVCC(5)

DVIO(6)

Type

UART,

SPI, I2C

(Ch)

IrDA,

SPI

64 RGC

10 ext,

MSP430F5259

128

5, 3, 3

64 YFF (7)

I2C

2 int

80 ZQE

64 RGC

MSP430F5258

128

5, 3, 3

N/A

I2C

80 ZQE

10 ext,

64 RGC

MSP430F5257

128

5, 3, 3

I2C

2 int

80 ZQE

64 RGC

MSP430F5256

128

5, 3, 3

N/A

I2C

80 ZQE

10 ext,

64 RGC

MSP430F5255

128

5, 3, 3

UART

2 int

80 ZQE

64 RGC

MSP430F5254

128

5, 3, 3

N/A

UART

80 ZQE

10 ext,

64 RGC

MSP430F5253

128

5, 3, 3

UART

2 int

80 ZQE

64 RGC

MSP430F5252

128

5, 3, 3

N/A

UART

80 ZQE

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/packaging.

(3)

Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(4)

Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(5)

All of these I/O reside on a single voltage rail supplied by DVCC.

(6)

All of these I/O reside on a single voltage rail supplied by DVIO.

(7)

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