MSP430F5259 datasheet(12/107 Pages) TI1

12 / 107 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903A – MAY 2013 – REVISED JULY 2013

www.ti.com

Table 3. Terminal Functions (continued)

TERMINAL

NO.

I/O(1)

DESCRIPTION

NAME

RGC

ZQE

YFF

Reset input active low(14)

RSTDVCC/SBWTDIO(13)

I/O

Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated

General-purpose digital I/O with port interrupt

TA2 clock signal TA2CLK input

P6.0/TA2CLK/SMCLK/CB0/A0

I/O

SMCLK output

Comparator_B input CB0

Analog input A0 – ADC (not available on all device types)

General-purpose digital I/O with port interrupt

TA2 CCR0 capture: CCI0A input, compare: Out0 output

P6.1/TA2.0/CB1/A1

I/O

Comparator_B input CB1

Analog input A1 – ADC (not available on all device types)

BSL transmit output

General-purpose digital I/O with port interrupt

TA2 CCR1 capture: CCI1A input, compare: Out1 output

P6.2/TA2.1/CB2/A2

I/O

Comparator_B input CB2

Analog input A2 – ADC (not available on all device types)

BSL receive input

General-purpose digital I/O with port interrupt

TA2 CCR2 capture: CCI2A input, compare: Out2 output

P6.3/TA2.2/CB3/A3

I/O

Comparator_B input CB3

Analog input A3 – ADC (not available on all device types)

Reserved

N/A

(15)

N/A

Reserved

QFN Pad

Pad

N/A

QFN package pad. Connection to VSS recommended.

(14) This non-configurable reset resides on the DVCC supply domain and has an internal pullup to DVCC. When driven from external, input

swing levels from DVSS to DVCC are required. This reset must be used for Spy-Bi-Wire communication and is not the same RST/MNI

reset as found on other devices in the MSP430 family. Refer to Bootstrap Loader - I2C and JTAG Operation for details regarding the

use of this pin.

(15) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.

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