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GMS90C31 数据表(PDF) 45 Page - Hynix Semiconductor |
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GMS90C31 数据表(HTML) 45 Page - Hynix Semiconductor |
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45 / 59 page ![]() GMS90 Series Oct. 2000 Ver 3.1a 41 AC Characteristics for GMS90 series (40MHz) External Data Memory Characteristics Advance Information (40MHz) External Clock Drive Parameter Symbol at 40 MHz Clock Variable Clock 1/tCLCL =3.5 to 40MHz Unit Min. Max. Min. Max. RD pulse width tRLRH 120 - 6tCLCL-30 - ns WR pulse width tWLWH 120 - 6tCLCL-30 - ns Address hold after ALE tLLAX2 10 - tCLCL-15 - ns RD to valid data in tRLDV -75 - 5tCLCL-50 ns Data hold after RD tRHDX 0- 0 - ns Data float after RD tRHDZ -38 - 2tCLCL-12 ns ALE to valid data in tLLDV -150 - 8tCLCL-50 ns Address to valid data in tAVDV -150 - 9tCLCL-75 ns ALE to WR or RD tLLWL 60 90 3tCLCL-15 3tCLCL+15 ns Address valid to WR or RD tAVWL 70 - 4tCLCL-30 - ns WR or RD high to ALE high tWHLH 10 40 tCLCL-15 tCLCL+15 ns Data valid to WR transition tQVWX 5- tCLCL-20 - ns Data setup before WR tQVWH 125 - 7tCLCL-50 - ns Data hold after WR tWHQX 5- tCLCL-20 - ns Address float after RD tRLAZ -0 - 0 ns Parameter Symbol Variable Oscillator (Freq. = 3.5 to 40MHz) Unit Min. Max. Oscillator period tCLCL 25 285.7 ns High time tCHCX 10 tCLCL -tCLCX ns Low time tCLCX 10 tCLCL -tCHCX ns Rise time tCLCH -10 ns Fall time tCHCL -10 ns |
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