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80960JD 数据表(PDF) 32 Page - Intel Corporation

部件名 80960JD
功能描述  EMBEDDED 32-BIT MICROPROCESSOR
PDF  61 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

80960JD 数据表(HTML) 32 Page - Intel Corporation

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PRELIMINARY
80960JD
Table 16. Note Definitions for Table 15, 80960JD AC Characteristics (50 MHz) (pg. 26)
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recog-
nition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
10. Relative to falling edge of TCK.
Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 1 of 3)
Symbol
Parameter
Min
Max
Units
Notes
INPUT CLOCK TIMINGS
TF
CLKIN Frequency
8
20
MHz
TC
CLKIN Period
50
125
ns
T
CS
CLKIN Period Stability
±250
ps
(1, 2)
TCH
CLKIN High Time
20
ns
Measured at
1.5 V (1)
TCL
CLKIN Low Time
20
ns
Measured at
1.5 V (1)
T
CR
CLKIN Rise Time
7
ns
0.8 V to 2.0
V (1)
TCF
CLKIN Fall Time
7
ns
2.0 V to 0.8
V (1)
SYNCHRONOUS OUTPUT TIMINGS
T
OV1
Output Valid Delay, Except ALE/ALE
Inactive and DT/R
3.5
18
ns
(3)



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