80960JD datasheet(5/61 Pages) INTEL

5 / 61 page

80960JD

PRELIMINARY

1.0

PURPOSE

This document contains advance information for the

80960JD

microprocessor,

including

electrical

characteristics

and

package

pinout

information.

Detailed

functional

descriptions

—

other

than

parametric performance — are published in the

i960

® Jx Microprocessor User’s Guide (272483).

Throughout this data sheet, references to “80960Jx”

indicate features which apply to all of the following:

• 80960JA — 5V, 2 Kbyte instruction cache, 1 Kbyte

data cache

• 80960JF — 5V, 4 Kbyte instruction cache, 2 Kbyte

data cache

• 80960JD — 5V, 4 Kbyte instruction cache, 2 Kbyte

data cache and clock doubling

• 80L960JA — 3.3 V version of the 80960JA

• 80L960JF — 3.3 V version of the 80960JF

2.0

80960JD OVERVIEW

The 80960JD offers high performance to cost-

sensitive

32-bit

embedded

applications.

The

80960JD is object code compatible with the 80960

Core Architecture and is capable of sustained

execution at the rate of one instruction per clock.

This

processor’s

features

include

generous

instruction cache, data cache and data RAM. It also

boasts a fast interrupt mechanism, dual program-

mable timer units and new instructions.

The 80960JD’s clock doubler operates the processor

core at twice the bus clock rate to improve execution

performance without increasing the complexity of

board designs.

Memory subsystems for cost-sensitive embedded

applications often impose substantial wait state

penalties. The 80960JD integrates considerable

storage

resources

on-chip

decouple

CPU

execution from the external bus.

The 80960JD rapidly allocates and deallocates local

needs to flush a register set to the stack only when it

saves more than seven sets to its local register

cache.

A 32-bit multiplexed burst bus provides a high-speed

interface

system

memory

and

I/O.

full

complement

control

signals

simplifies

the

connection of the 80960JD to external components.

The user programs physical and logical memory

attributes through memory-mapped control registers

(MMRs) — an extension not found on the i960 Kx,

Sx or Cx processors. Physical and logical configu-

ration registers enable the processor to operate with

all combinations of bus width and data object

alignment. The processor supports a homogeneous

byte ordering model.

This processor integrates two important peripherals:

a timer unit and an interrupt controller. These and

other hardware resources are programmed through

memory-mapped control registers, an extension to

the familiar 80960 architecture.

The timer unit (TU) offers two independent 32-bit

timers for use as real-time system clocks and

general-purpose system timing. These operate in

either single-shot or auto-reload mode and can

generate interrupts.

The interrupt controller unit (ICU) provides a flexible

means for requesting interrupts. The ICU provides

full programmability of up to 240 interrupt sources

into 31 priority levels. The ICU takes advantage of a

cached priority table and optional routine caching to

minimize interrupt latency. Clock doubling reduces

interrupt

latency

40%

compared

the

80960JA/JF. Local registers may be dedicated to

high-priority interrupts to further reduce latency.

Acting

independently

from

the

core,

the

ICU

compares the priorities of posted interrupts with the

current process priority, off-loading this task from the

core. The ICU also supports the integrated timer

interrupts.

The 80960JD features a Halt mode designed to

support applications where low power consumption

is critical. The halt instruction shuts down instruction

execution, resulting in a power savings of up to 90

percent.

The 80960JD’s testability features, including ONCE

(On-Circuit Emulation) mode and Boundary Scan

(JTAG), provide a powerful environment for design

debug and fault diagnosis.

The Solutions960® program features a wide variety

development

tools

which

support

the

i960

processor family. Many of these tools are developed

by partner companies; some are developed by Intel,

such as profile-driven optimizing compilers. For more

information on these products, contact your local

Intel representative.

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