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80960JD 数据表(PDF) 1 Page - Intel Corporation

部件名 80960JD
功能描述  EMBEDDED 32-BIT MICROPROCESSOR
PDF  61 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

80960JD 数据表(HTML) 1 Page - Intel Corporation

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Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995
September 1995
Order Number: 272596-002
PRELIMINARY
80960JD
EMBEDDED 32-BIT MICROPROCESSOR
Figure 1. 80960JD Microprocessor
s
Pin/Code Compatible with all 80960Jx
Processors
s
High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Core Clock Rate is 2x the Bus Clock
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
s
Two-Way Set Associative Instruction Cache
— 80960JD - 4 Kbyte
— Programmable Cache Locking
Mechanism
s
Direct Mapped Data Cache
— 80960JD - 2 Kbyte
— Write Through Operation
s
On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
s
On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
s
High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
s
New Instructions
— Conditional Add, Subtract and Select
— Processor Management
s
High-Speed Interrupt Controller
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
s
Two On-Chip Timers
— Independent 32-Bit Counting
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
s
Halt Mode for Low Power
s
IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
s
Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack (PQFP)
PIN 1
132
99
66
33
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© 19xx
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