AN4192 datasheet(9/47 Pages) STMICROELECTRONICS

9 / 47 page

AN4192

High-side MOSFET selection

Doc ID 023820 Rev 1

9/47

High-side MOSFET selection

For the right choice of high-side FET, the following MOSFET electrical parameters must be

considered:

Qg (total gate charge): it impacts the HS switching speed (at turn-on and turn-off) and

then the switching losses. Moreover, slightly bigger intrinsic capacitances, slowing

down the HS turn-on, may smooth the phase node ringing (overshoot and high

frequency oscillations on the phase node at HS turn-on).

RDS(on) (ON-state drain-source resistance): when the converter duty cycle is low, the

HS stays on for a short time, so the minimization of RDS(on) doesn't impact greatly on

the efficiency. However, the higher the VRM output voltage (i.e. there are 3.3 V or 5 V

sections in the notebook platforms), the bigger the RDS(on) impact.

RG,HS (external gate resistance) and gate drive network settings: the right RG,HS value

should be a trade-off between high switching speed and efficiency (low RG,HS) and the

phase node ringing improvement (high RG,HS). Some gate drive network

configurations, such as “asymmetric gate drive”, are able to enhance the converter

switching behavior with limited consequences on the efficiency.

Figure 4.

Gate charge waveform

In Figure 4, the simplified gate charge waveform for N-MOS (neglecting the parasitic effects)

is illustrated, which represents the VGS behavior as a function of time. The switching

transient is the interval [t0,t2], when vDS(t) and iD(t) are simultaneously bigger than zero. At t

= t0, the gate-source capacitance (Cgs) is charged and the drain current starts to increase.

During [t0,t1], the drain current increases linearly until it reaches its final value (IOUT). At t =

t1, the gate-source capacitance (Cgs) is totally charged, the drain-source voltage begins to

fall (we assume that the falling edge is linear) and the gate current flows through the Miller

(or transfer) capacitance. For t > t2, the switching losses are negligible because the

MOSFET is in the ohmic zone, with a constant RDS(on).

The charge amount QG,SW = QGD + QGS2 is needed to turn on the FET: it is also called

“switching charge”. The high-side FET switching losses (for a single-phase synchronous

buck converter) can be expressed as:

Equation 1

AM16448V1

---

OUT

GSW

GATE

--------------------

⋅⋅

⋅

AN4192 数据表(PDF) 9 Page - STMicroelectronics

AN4192 数据表(HTML) 9 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

数据表下载