AN2784

Overview of the STM32F10xxx flexible static memory controller

Doc ID 14779 Rev 4

7/31

Figure 2.

FSMC memory banks

1.1

Interfacing asynchronous static memories (NOR Flash,

SRAM)

The interface signals are synchronized by the internal clock HCLK. This clock is not output

to the memory

The FSMC always samples the data before de-asserting the chip select signal NE. This

guarantees that the memory data-hold timing constraint is met (chip enable high to data

transition, usually 0 ns min.).

●

If extended mode is enabled (EXTMOD: bit is set in the FSMC_BCRx register), there

are up to four extended modes (A, B, C and D) and it is possible to mix modes A, B, C

and D in read and write access.

●

If Extended mode is disabled, the FSMC operates in Mode1 or Mode2 as follows:

–

Mode 1 is the default mode when SRAM/CRAM memory type is selected ( Bits 3:2

MTYP = 0x0 or 0x01 in the FSMC_BCRx register)

–

Mode 2 is the default mode when NOR memory type is selected ( Bits 3:2 MTYP =

0x10 in the FSMC_BCRx register) "

Bank 1

NAND Flash

NOR / PSRAM

Supported memory type

Banks

4 × 64 MB

6000 0000h

6FF F FFF Fh

Address

7000 0000h

7FF F FFF Fh

8000 0000h

8FF F FFF Fh

9000 0000h

9FF F FFF Fh

Bank 2

4 × 64 MB

Bank 3

4 × 64 MB

Bank 4

4 × 64 MB

PC Card

ai14719