AN2784

Interfacing with an 8-bit NAND Flash memory

Doc ID 14779 Rev 4

23/31

Bank2 is selected to support the NAND Flash device. Based on these data, the FSMC is

configured as follows:

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Bank2 is enabled: PCR2_PBKEN bit set to ‘1’

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Memory type is NAND Flash: PCR2_PTYP is set to ‘1’ to select the NAND Flash

memory type.

●

Databus width is 8 bit: PCR2_PWID is set to ‘00’ to select 8-bit width.

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ECC page size is 512 bytes: PCR2_ECCPS is set to ‘001’ to set the ECC computation

page size to 512 bytes.

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ECC hardware calculation on/off as needed: PCR2_ECCEN is set or reset accordingly.

●

Wait feature may or not be enabled depending on the user’s application:

PCR2_PWAITEN is set or reset as needed.

The Ready/Busy memory signal can be connected to the FSMC_NWAIT pin, and in this

case the Wait feature must be used to manage the NAND Flash operations.

When using the NAND Flash memory with the wait feature enabled, the controller waits for

the NAND Flash to be ready to become active before starting a new access. While waiting,

the controller maintains the NCE signal active (low).

Generally, the Ready/Busy signal is an open-drain output. To connect this signal to the

STM32F10xxx microcontroller, the corresponding pin must be configured as input pull-up.

The Ready/Busy signal can be used as an interrupt source for the FSMC and, in this case,

the CPU can perform other tasks during NAND Flash operations.

Three FSMC configurations make it possible to use this signal as an interrupt. For that

purpose, the IREN, IFEN or ILEN bits in the SR2 register are used to select the rising edge,

the falling edge or the high level of the NAND Flash Ready/Busy signal.

4.2

Timing computation

Besides configuring the different features that are to be used with the NAND Flash memory,

the user has to initialize the controller to meet the memory timings.

As described in Section 4.1, the FSMC is able to program four different timings for the

common space and the attribute space independently: Setup time, Wait time, Hold time

and Databus HiZ time.

These parameters are computed according to the NAND Flash memory characteristics and

the STM32F10xxx HCLK clock.