AN2784

Overview of the STM32F10xxx flexible static memory controller

Doc ID 14779 Rev 4

5/31

1

Overview of the STM32F10xxx flexible static memory

controller

The FSMC has the following main features:

●

Interfaces with static memory-mapped devices including:

–

Static random access memory (SRAM)

–

Read-only memory (ROM)

–

NOR Flash memory

–

PSRAM (4 memory banks)

●

Two banks of NAND Flash with ECC hardware that checks up to 8 Kbytes of data

●

16-bit PC Card compatible devices

●

Supports burst mode access to synchronous devices (NOR Flash and PSRAM)

●

8- or 16-bit wide databus

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Independent chip select control for each memory bank

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Independent configuration for each memory bank

●

Programmable timings to support a wide range of devices, in particular:

–

Programmable wait states (up to 15)

–

Programmable bus turnaround cycles (up to 15)

–

Programmable output enable and write enable delays (up to 15)

–

Independent read and write timings and protocol, so as to support the widest

variety of memories and timings

●

Write enable and byte lane select outputs for use with PSRAM and SRAM devices

●

Translation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to

external 16-bit or 8-bit devices

●

A Write FIFO, 2 words long, each word is 32 bits wide, only stores data and not the

address. Therefore, this FIFO only buffers AHB write burst transactions. This makes it

possible to write to slow memories and free the AHB quickly for other operations. Only

one burst at a time is buffered: if a new AHB burst or single transaction occurs while an

operation is in progress, first the FIFO is drained ( The FSMC will insert wait states until

the current memory access is complete).

●

External asynchronous wait control

The FSMC registers that define the external device type and associated characteristics are

usually set at boot time and do not change until the next reset or power-up. However, it is

possible to change the settings at any time.

Figure 1 illustrates the FSMC block diagram.