AN2784

Interfacing with an 8-bit NAND Flash memory

Doc ID 14779 Rev 4

21/31

4.1

FSMC configuration

To control a NAND Flash memory, the FSMC provides the following possible features:

●

Enable or disable the use of the memory Ready/Busy signal as the wait input for the

FSMC.

●

Enable or disable the use of the memory Ready/Busy signal as the interrupt source for

the FSMC: the interrupt can be generated with three possible configurations:

–

on the rising edge of the Ready/Busy signal: when the memory has just completed

an operation and the new status in ready.

–

on the falling edge of the Ready/Busy signal: when the memory starts the new

operation

–

on the high level of the Ready/Busy signal: when the memory is ready.

●

Select the NAND Flash databus width: 8- or 16-bit width.

●

Enable or disable the ECC computation logic.

●

Specify the ECC page size: it can be 256, 512, 1024, 2048, 4096 or 8192 bytes.

The FSMC also provides the possibility of programming the timings for the different NAND

Flash sections separately: common section and attribute section. The timings are the

following:

●

Setup time: it is the time (in HCLK) required to set up the address before the command

assertion. That is, It is the time from address valid to the start of the read or write

operation.

●

Wait time: It is the time (in HCLK) required to assert the command. That is, it is the

time taken by the NOE and NWE signals to become deasserted.

●

Hold time: it is the time (in HCLK) during which the address is held after the command

deassertion. That is, it is the time between the deassertion of the NOE and NWE

signals and the end of the operation cycle.

●

Databus HiZ time: it is only valid for write operations and corresponds to the time (in

HCLK) during which the databus is kept in the high-impedance state after the start of a

write access. That is, it is the time from address valid to databus driven.

Figure 10 shows the different timings for a typical NAND Flash memory access.