AN3232

Exceptional thermal performance potential of the STAC package concept

Doc ID 17594 Rev 3

7/26

2

Exceptional thermal performance potential of the

STAC package concept

RF Power transistors are made up of hundreds of thousands of heat generating cells,

organized in an ultra-compact geometry at the silicon chip level. The necessity to generate

RF power at ever-increasing frequencies leads directly to the shrinking of silicon geometries

to ever-smaller portions of electrical wavelength. The result is unprecedented power density,

unmatched by most devices in the semiconductor industry. Indeed, such a power density

approaches those frequently encountered in the realm of high-energy physics.

The highest priority of the power transistor package is efficient evacuation of the incredible

thermal flux from the active regions of semiconductor chips to the external environment.

Great advances made to improve packaging systems and materials have enhanced this

effect, including the use of high thermal conductivity materials, the reduction of thermal path

length, and the improvement of thermal interfaces by way of superior flatness coupled with

enhanced TIMs.

A demonstration of the high power density of one device in the STAC family is shown in

Figure 3 by way of infrared imaging. In this example, the junction temperature of the

semiconductor chips, dissipating a total of 400 W continuously, is maintained uniformly

below the maximum allowable temperature of 200 °C, while the case is elevated almost to

its maximum of 85 °C.

Figure 3.

Infrared imaging of a STAC package

As is the case with many RF power devices, thermal resistance is dominated by the chips

themselves, as can be ascertained in Figure 3. In addition, the thermal conductivity of

silicon decreases with increasing temperature, therefore it is common practice to evaluate

power transistors near the maximum operating temperatures. Taking this into account, the