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MPC8264AVR 数据表(PDF) 46 Page - Motorola, Inc

部件名 MPC8264AVR
功能描述  MPC826xA (HiP4) Family Hardware Specifications
PDF  48 Pages
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制造商  MOTOROLA [Motorola, Inc]
网页  http://www.freescale.com
标志 MOTOROLA - Motorola, Inc

MPC8264AVR 数据表(HTML) 46 Page - Motorola, Inc

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MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
Document Revision History
0.5
3/2002
• Table 19: Modified notes to pins AE11 and AF25.
• Table 19: Addition of note to pins AA1 and AG4 (Therm0 and Therm1).
0.6
3/2002
• Table 19: Modified notes to pins AE11 and AF25.
0.7
5/2002
• Section 1.1, “Features”: minimum supported core frequency of 150 MHz
• Section 1.1, “Features”: updated performance values (under “Dual-issue integer core”)
• Table 2: Note 2 (changes in italics): “...less than or equal to 233 MHz, 166 MHz CPM...”
• Table 2: Addition of note 3.
0.8
1/2003
• Table 2: Modification to supply voltage ranges reflected in notes 2, 3, and 4.
• Table 4: Addition of
θJB and θJC.
• Table 7, Figure 8: Addition of sp42a/sp43a.
• Figure 3, Figure 4: Addition of note for FCC output.
• Figure 5, Figure 6, Figure 7: Addition of notes.
• Table 13, Table 16, and Table 18: Removal of PLL bypass mode from clock tables.
0.9
8/2003
• Note: In revision 0.3, sp30 (Table 10) was changed. This change was not previously recorded
in this “Document Revision History” Table.
• Removal of “HiP4 PowerQUICC II Documentation” table. These supplemental specifications
have been replaced by revision 1 of the MPC8260 PowerQUICC II™ Family Reference
Manual.
• Figure 1 and Section 1.1, “Features”: Addition of MPC8255 notes
• Addition of Figure 2
• Addition of VCCSYN to “Note: Core, PLL, and I/O Supply Voltages” following Table 2
• Addition of note 1 to Table 3
• Table 4: Changes to
θJA and θJB and θJC.
• Addition of notes or modifications to Figure 6, Figure 7, and Figure 8
• Table 9: Change of sp10.
• Addition of Table 14.
• Addition of note 2 to Table 19
• Table 19: Addition of FCC2 Rx and Tx [3,4] to CPM pins PD7, PD18, PD19, and PD29. Also,
the addition of SPICLK to PC19. They are documented correctly in the parallel I/O ports
chapter in the MPC8260 PowerQUICC II™ Family Reference Manual but had previously
been omitted from Table 19.
Table 22. Document Revision History (Continued)
Revision
Date
Substantive Changes



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