EM346-RTR datasheet(50/142 Pages) SILABS

50 / 142 page

EM346

Rev 1.0

7.3. Forced Functions

For some GPIOs, the GPIO_PxCFGH/L configuration will be overridden. These functions are forced when the

EM346 is reset and remain forced until software overrides the forced functions. Table 7.2 shows the GPIOs that

have different functions forced on them regardless of the GPIO_PxCFGH/L registers.

PA7 is forced to be the regulator enable signal, REG_EN. If an external regulator is used and controlled through

REG_EN, PA7’s forced functionality must not be overridden. If an external regulator is not used, REG_EN may be

disabled and PA7 may be reclaimed as a normal GPIO. Disabling REG_EN is done by clearing the bit

GPIO_EXTREGEN in the GPIO_DBGCFG register.

PC0, PC2, PC3, and PC4 are forced to be the Serial Wire and JTAG (SWJ) Interface. When the EM346 resets,

these four GPIOs are forced to operate in JTAG mode. Switching the debug interface between JTAG mode and

Serial Wire mode can only be accomplished by the external debug tool and cannot be affected by software

executing on the EM346. Due to the fact that Serial Wire mode can only be invoked by an external debug tool and

JTAG mode is forced when the EM346 resets, a designer must treat all four debug GPIOs as working in unison

even though the Serial Wire interface only uses one of the GPIO, PC4.

Note: An application must disable all debug SWJ debug functionality to reclaim any of the four GPIOs: PC0, PC2, PC3, and

PC4. Disabling SWJ debug functionality prevents external debug tools from operating, including flash programming and

high-level debug tools.

Disabling the SWJ debugger interface is accomplished by setting the GPIO_DEBUGDIS bit in the GPIO_DBGCFG

SWJ debugger interface is already active, the bit GPIO_DEBUGDIS cannot be set. When GPIO_DEBUGDIS is

set, the SWJ debugger interface can be reclaimed by activating the SWJ while the EM346 is held in reset. If the

SWJ debugger interface is forced active in this manner, the bit GPIO_FORCEDBG is set in the GPIO_DBGSTAT

port’s CRTL/STAT register in the SWJ, is set high by an external debug tool.

7.4. Reset

A full chip reset is one due to power on (low or high voltage), the nRESET pin, the watchdog, or the

SYSRESETREQ bit. A full chip reset affects the GPIO configuration as follows:



The GPIO_PxCFGH/L configurations of all pins are configured as floating inputs.



The GPIO_EXTREGEN bit is set in the GPIO_DBGCFG register, which overrides the normal configuration

for PA7.



The GPIO_DEBUGDIS bit in the GPIO_DBGCFG register is cleared, allowing Serial Wire/JTAG access to

override the normal configuration of PC0, PC2, PC3, and PC4.

Table 7.2. GPIO Forced Functions

GPIO

Forced Mode

Forced Signal

PA7

Open-drain output

REG_EN

PC0

Input with pull up

JRST

PC2

Push-pull output

JTDO

PC3

Input with pull up

JDTI

PC4*

Input with pull up

JTMS

PC4*

Bidirectional (push-pull output or floating input) controlled by debugger interface

SWDIO

*Note: The choice of PC4’s forced signal is controlled by an external debug tool. JTMS is forced when the SWJ is in JTAG

mode, and SWDIO is forced when the SWJ is in Serial Wire mode.

EM346-RTR 数据表(PDF) 50 Page - Silicon Laboratories

EM346-RTR 数据表(HTML) 50 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

EM346-RTR 数据表(PDF) 50 Page - Silicon Laboratories

EM346-RTR 数据表(HTML) 50 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载