EM346-RTR datasheet(53/142 Pages) SILABS

53 / 142 page

EM346

Rev 1.0

triggers a wake event.) Hardware records the fact that GPIO activity caused a wake event, but not which specific

GPIO was responsible. Instead, the Ember software reads the state of the GPIOs on waking to determine this.

The register GPIO_WAKEFILT contains bits to enable digital filtering of the external wakeup event sources: the

GPIO pins, SC1 activity, and IRQD. The digital filter operates by taking samples based on the (nominal) 10 kHz RC

oscillator. If three samples in a row all have the same logic value, and this sampled logic value is different from the

logic value seen upon entering sleep, the filter outputs a wakeup event.

In order to use GPIO pins to wake the EM346 from deep sleep, the GPIO_WAKE bit in the WAKE_SEL register

must be set. Waking up from GPIO activity does not work with pins configured for analog mode since the digital

logic input is always set to 1 when in analog mode. Refer to "6. System Modules" on page 33 for information on the

EM346’s power management and sleep modes.

7.8. External Interrupts

The EM346 can use up to three external interrupt sources (IRQA, IRQC, and IRQD), each with its own top-level

NVIC interrupt vector. Since these external interrupt sources connect to the standard GPIO input path, an external

interrupt pin may simultaneously be used by a peripheral device or even configured as an output. Analog mode is

the only GPIO configuration that is not compatible with using a pin as an external interrupt.

External interrupts have individual triggering and filtering options selected using the registers GPIO_INTCFGA,

GPIO_INTCFGB, GPIO_INTCFGC, and GPIO_INTCFGD. The bit field GPIO_INTMOD of the GPIO_INTCFGx

falling edge; 3 for both edges; 4 for active high level; 5 for active low level. The minimum width needed to latch an

unfiltered external interrupt in both level- and edge-triggered mode is 80 ns. With the digital filter enabled (the

GPIO_INTFILT bit in the GPIO_INTCFGx register is set), the minimum width needed is 450 ns.

The register INT_GPIOFLAG is the second-level interrupt flag register that indicates pending external interrupts.

Writing 1 to a bit in the INT_GPIOFLAG register clears the flag while writing 0 has no effect. If the interrupt is level-

triggered, the flag bit is set again immediately after being cleared if its input is still in the active state.

IRQA has a fixed pin assignment. The other two external interrupts, IRQC and IRQD, can use any GPIO pin. The

GPIO_IRQCSEL and GPIO_IRQDSEL registers specify the GPIO pins assigned to IRQC and IRQD, respectively.

Table 7.3 shows how the GPIO_IRQCSEL and GPIO_IRQDSEL register values select the GPIO pin used for the

external interrupt.

In some cases, it may be useful to assign IRQC or IRQD to an input also in use by a peripheral, for example to

generate an interrupt from the slave select signal (nSSEL) in an SPI slave mode interface.

Refer to "9. Interrupt System" on page 100 for further information regarding the EM346 interrupt system.

7.9. Debug Control and Status

Two GPIO registers are largely concerned with debugger functions. GPIO_DBGCFG can disable debugger

Table 7.3. IRQC/D GPIO Selection

GPIO_IRQxSEL

GPIO

GPIO_IRQxSEL

GPIO

GPIO_IRQxSEL

GPIO

PA4

PB0

PC0

PA5

PB1

PC1

PA7

PB2

PC2

PB3

PC3

PB4

PC4

PC5

PC6

PC7

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