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EM346-RTR 数据表(PDF) 74 Page - Silicon Laboratories |
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EM346-RTR 数据表(HTML) 74 Page - Silicon Laboratories |
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74 / 142 page  EM346 Rev 1.0 75 8.3.2. Set Up and Configuration The serial controller, SC1, supports SPI slave mode. SPI slave mode is enabled by the following register settings: The serial controller mode register, SCx_MODE, is 2 The SC_SPIMST bit in the SPI configuration register, SCx_SPICFG, is 0 The SPI slave controller receives its clock from an external SPI master device and supports rates up to 5 Mbps. The SPI slave controller supports various frame formats depending upon the clock polarity (SC_SPIPOL), clock phase (SC_SPIPHA), and direction of data (SC_SPIORD) (see Table 8.3). The SC_SPIPOL, SC_SPIPHA, and SC_SPIORD bits are defined within the SCx_SPICFG registers. Table 8.3. SPI Slave Formats SCx_SPICFG Frame Format SC_SPIxxx* MST ORD PHA POL 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 — — Same as above except LSB first instead of MSB first *Note: The notation “xxx” means that the corresponding column header below is inserted to form the field name. TX[7] RX[7] TX[6] RX[6] TX[5] RX[5] TX[4] RX[4] TX[3] RX[3] TX[2] RX[2] TX[1] RX[1] TX[0] RX[0] nSSEL SCLKin MOSIin MISOout TX[7] RX[7] TX[6] RX[6] TX[5] RX[5] TX[4] RX[4] TX[3] RX[3] TX[2] RX[2] TX[1] RX[1] TX[0] RX[0] SCLKin MOSIin MISOout TX[7] RX[7] TX[6] RX[6] TX[5] RX[5] TX[4] RX[4] TX[3] RX[3] TX[2] RX[2] TX[1] RX[1] TX[0] RX[0] nSSEL SCLKin MOSIin MISOout TX[7] RX[7] TX[6] RX[6] TX[5] RX[5] TX[4] RX[4] TX[3] RX[3] TX[2] RX[2] TX[1] RX[1] TX[0] RX[0] nSSEL MOSIin MISOout SCLKin |
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