LAN8710AI datasheet(22/82 Pages) MICROCHIP

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Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

Datasheet

Revision 1.4 (08-23-12)

SMSC LAN8710A/LAN8710Ai

DATASHEET

3.1.1.6

100M Phase Lock Loop (PLL)

The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz

logic and the 100BASE-TX transmitter.

3.1.2

100BASE-TX Receive

The 100BASE-TX receive data path is shown in Figure 3.2. Each major block is explained in the

following subsections.

3.1.2.1

100M Receive Input

The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio

transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second.

Using a 64-level quanitizer, it generates 6 digital bits to represent each sample. The DSP adjusts the

gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC

can be used.

3.1.2.2

Equalizer, Baseline Wander Correction and Clock and Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates

for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,

and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m

and 150m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency

pole of the isolation transformer, then the droop characteristics of the transformer will become

significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the

received data, the transceiver corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD

defined “killer packet” with no bit errors.

Figure 3.2 100BASE-TX Receive Data Path

MAC

A/D

Converter

MLT-3

Converter

NRZI

Converter

4B/5B

Decoder

Magnetics

CAT-5

RJ45

PLL

MII 25Mhz by 4 bits

RMII 50Mhz by 2 bits

RX_CLK

(for MII only)

25MHz by

5 bits

NRZI

MLT-3

6 bit Data

Descrambler

and SIPO

125 Mbps Serial

DSP: Timing

recovery, Equalizer

and BLW Correction

MLT-3

MII/RMII

25MHz

by 4 bits

Ext Ref_CLK (for RMII only)

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