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USB3500 数据表(PDF) 22 Page - Microchip Technology

部件名 USB3500
功能描述  Hi-Speed USB Host, Device or OTG PHY
PDF  45 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

USB3500 数据表(HTML) 22 Page - Microchip Technology

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USB3500
DS00002103A-page 22
 2005 - 2016 Microchip Technology Inc.
5.5
Crystal Oscillator and PLL
The USB3500 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference clock that is
used by the PHY during both transmit and receive. The USB3500 requires a clean 24MHz crystal or clock as a frequency
reference. If the 24MHz reference is noisy or off frequency the PHY may not operate correctly.
The USB3500 can use either a crystal or an external clock oscillator for the 24MHz reference. The crystal is connected
to the XI and XO pins as shown in the application diagram, Figure 6-10. If a clock oscillator is used, the clock should be
connected to the XI input and the XO pin left floating. When using an external clock, the clock source must be clean so
it does not degrade performance, and should be driven with a 0 to 3.3 volt signal.
After the 480MHz PLL has locked to the correct frequency, it will drive the CLKOUT pin with a 60MHz clock. The
USB3500 is ensured to start the clock within the time specified in Table 4-2.
5.6
Internal Regulators and POR
The USB3500 includes integrated power management functions to reduce the bill of materials and simplify product
design.
5.6.1
INTERNAL REGULATORS
The USB3500 has two internal regulators that create two 1.8V outputs (labeled VDD1.8 and VDDA1.8) from the 3.3 volt
power supply input (VDD3.3). Each regulator requires an external 4.7uF +/-20% low ESR bypass capacitor to ensure
stability. X5R or X7R ceramic capacitors are recommended since they exhibit an ESR lower that 0.1ohm at frequencies
greater than 10kHz.
The specific capacitor recommendations for each pin are detailed in Table 2.1, "USB3500 Pin Locations", and shown in
Figure 6-10, "USB3500 Application Diagram (Top View)".
5.6.2
POWER ON RESET (POR)
The USB3500 provides an internal POR circuit that generates a reset pulse once the PHY supplies are stable. The
UTMI+ Digital can be reset at any time with the RESET pin.
5.7
USB On-The-Go (OTG) Module
The USB3500 provides support for USB OTG. This mode allows the USB3500 to be dynamically configured as a host
or a device depending on the type of cable inserted into the Mini-AB connector. When the Mini-A plug of a cable is
inserted into the Mini-AB connector the USB device becomes the A-device. When a Mini-B plug is inserted the device
becomes the B-device. The OTG A-device behaves similar to a Host while the B-device behaves similar to a peripheral.
The differences are covered in the OTG supplement.
The OTG Module meets all the requirements in the “On-The-Go Supplement to the USB 2.0 Specification”. In applica-
tions where only Host or Device is required, the OTG Module is unused.
Note:
The USB3500 regulators are designed to generate a 1.8volt supply for the USB3500 only. Using the reg-
ulators to provide current for other circuits is not recommended and Microchip does not ensure USB per-
formance or regulator stability in this case.



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