| 数据搜索系统,热门电子元器件搜索 |
|
USB3500 数据表(PDF) 7 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
USB3500 数据表(HTML) 7 Page - Microchip Technology |
|
7 / 45 page ![]() 2005 - 2016 Microchip Technology Inc. DS00002103A-page 7 USB3500 4 TXREADY Output High Transmit Data Ready. If TXVALID is asserted, the Link must always have data available for clocking into the TX Holding Register on the rising edge of CLKOUT. TXREADY is an acknowledgment to the Link that the transceiver has clocked the data from the bus and is ready for the next transfer on the bus. If TXVALID is negated, TXREADY can be ignored by the Link. 5 VBUS I/O, Analog N/A VBUS pin of the USB cable. 6 ID Input, Analog N/A ID pin of the USB cable. 7 SUSPENDN Input Low Suspend. Places the transceiver in a mode that draws minimal power from supplies. In host mode, RPU is removed during suspend. In device mode, RPD is controlled by TERMSEL. In suspend mode the clocks are off. 0: PHY in suspend mode 1: PHY in normal operation 8TXVALID Input High Transmit Valid. Indicates that the DATA bus is valid for transmit. The assertion of TXVALID initiates the transmission of SYNC on the USB bus. The negation of TXVALID initiates EOP on the USB. Control inputs (OPMODE[1:0], TERMSEL,XCVERSEL) must not be changed on the de-assertion or assertion of TXVALID. 9 RESET Input High Reset. Reset all state machines. After coming out of reset, must wait 5 rising edges of clock before asserting TXValid for transmit. Assertion of Reset: May be asynchronous to CLKOUT De-assertion of Reset: Must be synchronous to CLKOUT 10 VDD3.3 N/A N/A 3.3V PHY Supply. Provides power for USB 2.0 Transceiver, UTMI+ Digital, Digital I/O, and Regulators. 11 DP I/O, Analog N/A D+ pin of the USB cable. 12 DM I/O, Analog N/A D- pin of the USB cable. 13 VSS Ground N/A PHY ground. 14 VDD3.3 N/A N/A 3.3V PHY Supply. 15 XCVRSEL[1] Input N/A Transceiver Select. These signals select between the FS and HS transceivers: Transceiver select. 00: HS 01: FS 10: LS 11: LS data, FS rise/fall times 16 CHRGVBUS Input High Charge VBUS through a resistor to VDD3.3. 0: do not charge VBUS 1: charge VBUS 17 RXACTIVE Output High Receive Active. Indicates that the receive state machine has detected Start of Packet and is active. 18 OPMODE[1] Input N/A Operational Mode. These signals select between the various operational modes: [1] [0] Description 0 0 0: Normal Operation 0 1 1: Non-driving (all terminations removed) 1 0 2: Disable bit stuffing and NRZI encoding 1 1 3: Reserved 19 OPMODE[0] Input N/A TABLE 2-1: USB3500 PIN DEFINITIONS (CONTINUED) Pin Name Direction, Type Active Level Description |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |