USB3500

DS00002103A-page 32

6.10

HS Detection Handshake – Suspend Timing

If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver are assumed to be pow-

ered down. Figure 6-6 shows how CLKOUT is used to control the duration of the chirp generated by the device.

When reset is entered from a suspended state (J to SE0 transition reported by LINESTATE), SUSPENDN is combina-

torially negated at time T0 by the Link. It takes approximately 5 milliseconds for the transceiver's oscillator to stabilize.

The device does not generate any transitions of the CLKOUT signal until it is “usable” (where “usable” is defined as

stable to within ±10% of the nominal frequency and the duty cycle accuracy 50±5%).

The first transition of CLKOUT occurs at T1. The Link then sets OPMODE to Disable Bit Stuffing and NRZI encoding,

XCVRSELECT to HS mode, and must assert a Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration.

If CLKOUT is 10% fast (66MHz) then Chirp K will be 1.0ms. If CLKOUT is 10% slow (54 MHz) then Chirp K will be 1.2ms.

The 5.6ms requirement for the first CLKOUT transition after SUSPENDN, ensures enough time to assert a 1ms Chirp

K and still complete before T3. Once the Chirp K is completed (T3) the Link can begin looking for host chirps and use

CLKOUT to time the process. At this time, the device follows the same protocol as in Section 6.9, "HS Detection Hand-

shake – HS Downstream Facing Port" for completion of the High Speed Handshake.

TABLE 6-8:

RESET TIMING VALUES

Timing Parameter

Description

Value

T0

HS Handshake begins. DP pull-up enabled, HS

terminations disabled.

0 (reference)

T1

Device asserts Chirp K on the bus.

T0 < T1 < HS Reset T0 + 6.0ms

T2

Device removes Chirp K from the bus. 1 ms minimum

width.

T0 + 1.0ms < T2 <

HS Reset T0 + 7.0ms

T3

Downstream facing port asserts Chirp K on the bus. T2 < T3 < T2+100µs

T4

Downstream facing port toggles Chirp K to Chirp J on

the bus.

T3 + 40µs < T4 < T3 + 60µs

T5

Downstream facing port toggles Chirp J to Chirp K on

the bus.

T4 + 40µs < T5 < T4 + 60µs

T6

Device detects downstream port chirp.

T6

T7

Chirp detected by the device. Device removes DP

pull-up and asserts HS terminations, reverts to HS

default state and waits for end of reset.

T6 < T7 < T6 + 500µs

T8

Terminate host port Chirp K-J sequence (Repeating

T4 and T5)

T9 - 500µs < T8 < T9 - 100µs

T9

The earliest time at which host port may end reset.

The latest time, at which the device may remove the

DP pull-up and assert the HS terminations, reverts to

HS default state.

HS Reset T0 + 10ms

Note:

• T0 may be up to 4ms after HS Reset T0.

• The Link must use LINESTATE to detect the downstream port chirp sequence.

• Due to the assertion of the HS termination on the host port and FS termination on the device port, between T1

and T7 the signaling levels on the bus are higher than HS signaling levels and are less than FS signaling levels.