DS00002103A-page 25

USB3500

6.0

APPLICATION NOTES

The following sections consist of select functional explanations to aid in implementing the USB3500 into a system. For

complete description and specifications consult the USB 2.0 Transceiver Macrocell Interface Specification and Univer-

sal Serial Bus Specification Revision 2.0.

6.1

Linestate

The voltage thresholds that the LINESTATE[1:0] signals use to reflect the state of DP and DM depend on the state of

XCVRSELECT. LINESTATE[1:0] uses HS thresholds when the HS transceiver is enabled (XCVRSELECT = 0) and FS

thresholds when the FS transceiver is enabled (XCVRSELECT = 1). There is not a concept of variable single-ended

thresholds in the USB 2.0 specification for HS mode.

The HS receiver is used to detect Chirp J or K, where the output of the HS receiver is always qualified with the Squelch

signal. If squelched, the output of the HS receiver is ignored. In the USB3500, as an alternative to using variable thresh-

olds for the single-ended receivers, the following approach is used. In HS device mode, 3ms of no USB activity (IDLE

state) signals a reset. The Link monitors LINESTATE[1:0] for the IDLE state. To minimize transitions on LINESTATE[1:0]

while in HS mode, the presence of !Squelch is used to force LINESTATE[1:0] to a J state.

TABLE 6-1:

DEVICE LINESTATE STATES (DPPD & DMPD = 0)

State of DP/DM Lines

Linestate[1:0]

Full Speed

XCVRSELECT[1:0]=01

TERMSELECT=1

High Speed

XCVRSELECT[1:0]=00

TERMSELECT=0

Chirp Mode

XCVRSELECT[1:0]=00

TERMSELECT=1

LS[1]

LS[0]

0

0

SE0

Squelch

Squelch

0

1

FS-J

!Squelch

!Squelch &

HS Differential Receiver

Output

1

0

FS-K

Invalid

!Squelch &

!HS Differential Receiver

Output

1

1

SE1

Invalid

Invalid

TABLE 6-2:

HOST LINESTATE STATES (DPPD & DMPD = 1)

State of DPDM Lines

Linestate[1:0]

Low Speed

XCVRSEL[1:0]=10

TERMSELECT=1

Full Speed

XCVRSEL[1:0]=01

TERMSELECT=1

High Speed

XCVRSEL[1:0]=00

TERMSELECT=0

OPMODE=00/01

Chirp Mode

XCVRSEL[1:0]=00

TERMSELECT=0

OPMODE=10

LS[1]

LS[0]

0

0

SE0

SE0

Squelch

Squelch

0

1

LS-K

FS-J

!Squelch

!Squelch &

HS Differential

Receiver Output

1

0

LS-J

FS-K

Invalid

!Squelch &

!HS Differential

Receiver Output

1

1

SE1

SE1

Invalid

Invalid