M35B32 datasheet(21/44 Pages) STMICROELECTRONICS

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M35B32

Instructions

6.5

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

have been executed. After the Write Enable (WREN) instruction has been decoded and

executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,

followed by the instruction code and the data byte on Serial Data input (D).

The instruction sequence is shown in Figure 11.

The Write Status Register (WRSR) instruction has no effect on b7, b6, b1 and b0 of the

Status Register.

Chip Select (S) must be driven high after the eighth bit of the data byte has been latched in.

If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select

(S) is driven high, the self-timed Write Status Register cycle (whose duration is tW) is

initiated. While the Write Status Register cycle is in progress, the Status Register may still

be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)

bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user to change the values of the

Block Protect (BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated

as read only.

•

If the Write Protect pin (W) is driven high, it is possible to write to the Status Register

provided that the Write Enable Latch (WEL) bit has previously been set by a Write

Enable (WREN) instruction

•

If the Write Protect pin (W) is driven low, attempts to write the Status Register are not

executed (even if the Write Enable Latch (WEL) bit was previously set with a previous

Write Enable instruction). As a consequence, the size and the write protection status of

the Event sector (which size is defined by the (BP3, BP2, BP1, BP0) bits of the Status

Figure 11. Write Status Register (WRSR) instruction sequence

AI02282D

3456789 10 11 12 13 14 15

High Impedance

Instruction

Status

765432

MSB

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