M35B32 datasheet(29/44 Pages) STMICROELECTRONICS

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M35B32

Power-up and power-down

7.1

Supply voltage (VCC)

7.1.1

Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Table 6). In order to

secure a stable DC supply voltage, it is recommended to decouple the VCC line with a

suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package

pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for write, program and erase instructions, until the completion of the internal write,

program or erase cycle, respectively.

7.1.2

Power-up conditions

When the power supply is turned on, VCC continuously rises from VSS to VCC. During this

time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage, it is

therefore recommended to connect the S line to VCC via a suitable pull-up resistor.

In addition, the Chip Select (S) input offers a built-in safety feature, as this input is edge-

sensitive as well as level-sensitive: after power-up, the device does not become selected

until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select

(S) must have been high, prior to going low to start the first operation.

The VCC rise time must not vary faster than 1 V/µs.

7.1.3

Internal reset during power up

In order to prevent inadvertent write operations during power-up (continuous rise of VCC), a

power on reset (POR) circuit is included. At power-up, the device does not respond to any

instruction until the VCC has reached the power on reset threshold voltage (this threshold is

lower than the minimum VCC operating voltage defined in Table 6).

Until VCC has passed over the POR threshold, the device is reset, then the device is in the

following state:

•

Standby Power mode

•

deselected (at next power-up, a falling edge is required on Chip Select (S) before any

instruction can be started)

•

Status register:

–

the Write Enable Latch (WEL) is reset to 0

–

the Write In Progress (WIP) is reset to 0

The BP3, BP2, BP1 and BP0 bits of the Status Register are unchanged from the previous

power down (they are non-volatile bits).

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