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LNBH26LS 数据表(PDF) 17 Page - STMicroelectronics

部件名 LNBH26LS
功能描述  Dual LNBS supply and control IC with step-up and IC interface
PDF  33 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

LNBH26LS 数据表(HTML) 17 Page - STMicroelectronics

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LNBH26LS
I²C bus interface
DocID025504 Rev 1
17/33
6
I²C bus interface
Data transmission from the main microprocessor to the LNBH26LS, and vice versa, takes
place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up
resistors to positive supply voltage must be externally connected).
6.1
Data validity
As shown in Figure 7: "Data validity on the I²C bus", the data on the SDA line must be
stable during the high semi-period of the clock. The high and low state of the data line can
only change when the clock signal on the SCL line is low.
6.2
Start and stop condition
As shown in Figure 8: "Timing diagram of I²C bus", a start condition is a transition from high
to low of the SDA line while SCL is high. The stop condition is a transition from low to high
of the SDA line while SCL is high. A stop condition must be sent before than each start
condition.
6.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by
an acknowledge bit. The MSB is the first to be transferred.
6.4
Acknowledge
The master (microprocessor) puts a resistive high level on the SDA line during the
acknowledge clock pulse (see Figure 9: "Acknowledge on the I²C bus"). The peripheral
(LNBH26LS), which acknowledges, must pull down (low) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable low during this clock pulse. The
peripheral, which has been addressed, must generate acknowledge after the reception of
each byte, otherwise the SDA line remains at the high level during the ninth clock pulse
time. In this case, the master transmitter can generate the STOP information in order to
abort the transfer. The LNBH26LS doesn’t generate acknowledge if the V
CC supply is below
the undervoltage lockout threshold (4.7 V typ.).
6.5
Transmission without acknowledge
If the detection of LNBH26LS acknowledge is not necessary, the microprocessor can use a
simpler transmission; it simply waits for one clock without checking the slave
acknowledging, and sends the new data. This approach has less protection in case of
misworking and decreases noise immunity.



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