VD5377 datasheet(59/88 Pages) STMICROELECTRONICS

59 / 88 page

Doc ID 022952 Rev 2

59/88

VD5377

Image capture

In this mode, the pins BK0, BK1, BK2 and I2C_SEL0 are used for serial output of video data

in the form of 2 bits nibble + FST and QCLK.

Upon receipt of an FST (BK2) rising edge, NIB_EVEN (BK0) and NIB_ODD (BK1) output

data every 48 MHz clock cycle. The signals should be sampled the first rising CLK

(I2C_SEL0) edge after the FST rising edge, and then every rising CLK edge after that during

the 1600 cycles (400 x 4).

Groups of four consecutive NIB_EVEN and NIB_ODD must then be repackaged together to

form a single 8-bit pixel data. This format enables the pixels to be output at the same frame

rate as normal operation, and keeps I2C available to access the usual register settings.

Table 33. Fast capture

Addr

(Hex)

SIgnal name

Bit

Type

Default

(Hex)

Comment

SYSTEM_CONFIG

automatic_power_

mode

0PRW

Power mode scheme

0 = Manual

1 = Automatic

motion_pin_polarity

PRW

MOTION pin polarity (in non

IDLE system state)

0 = MOTION pin LOW when

motion detected

1 = MOTION pin HIGH when

motion detected

host_config_done

PRW

Bit needs to be set by host

when configured after power

up.

use_standby_pin

PRW

STANDBY pin is used as

chip select to enable I2C in

AUTO power mode and

STANDBY pin is used to

wake up the OSC/DVREG

(in sleep states in auto

power mode).

0 = STANDBY pin not used

1 = STANDBY pin is used

system_state

7:5

Legacy register - please use

system_state (0x91)

instead.

CLOCKS_LO

clk_motion_timer

PRW

Timer clock enabled (forced

always on)

clk_pci_en

PRW

PCI clock enable (forced

always on)

FRAMEDUMP_CTRL pci_test_enable

PRW

Muxed PCI data onto pads

(2 bits nibble + FST + Qclk)

0 = Disable

1 = Enable

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