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VD5377 数据表(PDF) 20 Page - STMicroelectronics |
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VD5377 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 88 page  System overview VD5377 20/88 Doc ID 022952 Rev 2 POWERDOWN pin is deasserted, the internal 1.8 V regulator is re-enabled triggering a POR (Power-On Reset) and the MCU re-initializes as at power-up before entering the SW STBY state. The device must be re-configured after POWERDOWN. Key timing parameters are shown in Table 9. Table 9. Manual mode timing constraints Symbol Parameter Typical t1 POR Delay (POR threshold = 1.4 V typ) 20 µs t2 Clock Startup 1 µs t3 MCU boot time 450 µs t4 Minimum Powerdown time (220 nF regulator capacitor) 10 ms t5(1) 1. No I2C comms permitted to VD5377 after Standby pin asserted Standby pin latency (up to 1 frame at 1 kf/s) up to 1 ms |
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