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VD5377 数据表(PDF) 43 Page - STMicroelectronics |
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VD5377 数据表(HTML) 43 Page - STMicroelectronics |
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43 / 88 page  Doc ID 022952 Rev 2 43/88 VD5377 Additional features Figure 18. BACKLED configuration BACKLED0 VTOP BACKLED1 BACKLED2 VD5377 BACKLED0 VTOP BACKLED1 BACKLED2 VD5377 x3 backlight LED scheme Single backlight LED scheme Table 26. BACKLED control registers Addr (Hex) Register name SIgnal name Bit Type Default (Hex) Comment 9 GPIO_BACKLED0 gpio_backled0_en 0 PRW 00 BACKLED0 output enable (active low) 0 = PAD configured as OUTPUT 1 = PAD configured as INPUT gpio_backled0_a 1 PRW 01 BACKLED0 data output (when _en = 0) gpio_backled0_zi 2 PR 01 BACKLED0 IO value gpio_backled0_tm 3 PRW 00 Reserved. Do not modify this bit. gpio_backled0_a_ ctrl 4PRW 00 BACKLED0 data output origin 0 = Output value from HW register 1 = Output value from PWM 0 gpio_backled0_ opendrain 7PRW 01 BACKLED0 pad open drain control 0 = BACKLED0 pad normal config 1 = BACKLED0 pad in open drain (A=EN) |
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