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UT699CPC 数据表(PDF) 28 Page - Aeroflex Circuit Technology |
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UT699CPC 数据表(HTML) 28 Page - Aeroflex Circuit Technology |
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28 / 41 page ![]() 28 4.5 Timing Characteristics SpaceWire Interface (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40 oC to 105oC) Notes: 1. The SPW_CLK frequency must be less than 4x the SYS_CLK frequency. For example, if SPW_CLK is running at 200MHz, the SYS_CLK frequency must be greater than 50MHz. 2. All outputs are measured using the load conditions shown in Figure 15. 3. Applies to both high pulse and low pulse. 4. A unit interval (UI) is defined as the nominal, or ideal, bit width. Figure 8. SpaceWire Transmit Timing Diagram Figure 9. SpaceWire Receive Timing Diagram Symbol Description Min Max Units t111 SPW_CLK period 5 -- ns t122 SPW_CLK to data delay (SPW_TXD[3:0]) 37 ns t132 SPW_CLK to strobe delay (SPW_TXS[3:0]) 37 ns t143 Transmit data and strobe bit width variation (SPW_TXD[3:0] and SPW_TXS[3:0]) UI-6004 UI+600 ps t153 Receive data and strobe bit width (SPW_RXD[3:0] and SPW_RXS[3:0]) 2.5 -- ns t16 Receive data and strobe edge separation (SPW_RXD[3:0] and SPW_RXS[3:0]) 2.5 -- ns t13 t13 t14 t14 t12 t12 t14 t14 t11 t11 SPW_CLK SPW_TXD SPW_TXS t15 t t16 t16 t15 t SPW_RXD SPW_RXS |
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