UT699CPC datasheet(24/41 Pages) AEROFLEX

24 / 41 page

Figure 4. Power Sequencing and Reset Timing Diagram

4.1.1. Power Sequencing

Proper power sequencing of the UT699 is achieved by bringing up VDD to its recommended minimum operating voltage of 3.0V,

and then delaying tVCD clock cycles before bringing up the VDDC supply. If power is applied to the VDDC supply pins while VDD

is less than 3.0V, excessive current or damage to the device could occur.

4.1.2 Bus Control and Bi-Direct Fail-Safe Circuitry

In order to prevent bus contention on the external memory interface while VDDC is ramping up, the UT699 has functionality to

ensure that the bi-direct and memory bus control signals described in Section 4.1 will be in a high-Z state tVHBZ clock cycles after

VDD reaches 1.5V. The core logic will then put these signals into their valid-inactive states tCHBV clock cycles after VDDC reaches

2.3V.

It is recommended that users place pull-up resistors on the indicated output enable, write enable, and chip select pins, and a pull-

down resistor on the READ pin, if there will be a significant delay between when VDD and VDDC reach their recommended operat-

ing voltages. This will prevent bus capacitance or transients from inadvertently placing these pins in an active state, which could

result in external memory devices driving the address and data buses.

4.1.3 Reset Circuitry

The reset circuitry is controlled by the core logic; therefore, the circuitry is functional only after VDDC reaches its minimum operat-

ing voltage of 2.3V. After VDDC is stable, the system must continue to assert RESET for a minimum of tRESET1 clock cycles before

it can be de-asserted. Asserting RESET for less time could result in the RESET signal not being recognized.

VALID-INACTIVE

VALID-ACTIVE

VALID-INACTIVE

VALID-ACTIVE

tRESET3

tVHBZ

tRESET3

tRESET2

tCHBV

tVHBZ

tRESET1

tVCD

SYSCLK

VDD 3.3V

VDDC 2.5V

RESET

Memory Bus

Tri-State Outputs

Control Signals

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