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UT699CPC 数据表(PDF) 20 Page - Aeroflex Circuit Technology |
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UT699CPC 数据表(HTML) 20 Page - Aeroflex Circuit Technology |
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20 / 41 page ![]() 20 3.6 AC Electrical Characteristics for LVCMOS3 Inputs and Outputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40 oC to 105oC) Notes: 1. Tested as shown in Figure 14. 2. Supplied as a design limit. Neither guaranteed nor tested. Figure 2. System Clock and SDCLK Timing Diagram Symbol Description Conditions Min Max Units fCLK System clock frequency -- 66 MHz tHIGH System clock high time 6.67 -- ns tLOW System clock low time 6.67 -- ns tDSD 1 System clock to SDRAM clock propagation delay 25 ns tRSD 2 SDRAM clock rise time fCLK = 66MHz VO transitioning between VOH (min) and VOL (max) -- 2 ns tFSD 2 SDRAM clock fall time fCLK = 66MHz VO transitioning between VOH (min) and VOL (max) -- 2 ns tJCCSD 2 SDRAM clock cycle-cycle jitter fCLK = 66MHz -- 500 ps tDSD tDSD 1/fCLK tLOW t tHIGH 1/f t SYSCLK SDCLK |
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