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UT699CPC 数据表(PDF) 3 Page - Aeroflex Circuit Technology |
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UT699CPC 数据表(HTML) 3 Page - Aeroflex Circuit Technology |
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3 / 41 page ![]() 3 2.0 Pin Identification and Description Pin Function Description I CMOS input IS CMOS input Schmitt O CMOS output I/O CMOS bi-direct OD CMOS open drain PCI-I PCI input PCI-O PCI output PCI-I/O PCI bi-direct PCI-3 PCI three-state 2.1. System Signals Notes: 1. This pin is actively driven low and must be tied to VDD through a pull-up resistor. 2.2 Address Bus Pin Name Function Pin Number Reset Value Description 352 CQFP 484 CLGA SYSCLK I 88 Y20 -- Main system clock RESET IS 136 L19 -- System reset ERROR1 OD 142 K19 -- Processor error mode indicator. This is an active low output. WDOG1 OD 145 J19 -- Watchdog indicator. This is an active low output. Pin Name Direction Pin Number Reset Value Description 352 CQFP 484 CLGA ADDR[0] O 1 W5 low Bit 0 of the address bus ADDR[1] O 2 Y5 low Bit 1 of the address bus ADDR[2] O 4 W6 low Bit 2 of the address bus ADDR[3] O 5 AA5 low Bit 3 of the address bus ADDR[4] O 6 Y6 low Bit 4 of the address bus ADDR[5] O 7 AB5 low Bit 5 of the address bus ADDR[6] O 9 W7 low Bit 6 of the address bus ADDR[7] O 10 AA6 low Bit 7 of the address bus ADDR[8] O 11 Y7 low Bit 8 of the address bus ADDR[9] O 12 AA7 low Bit 9 of the address bus |
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