25

signals ROMS[0] and OE will be driven to their valid-active states in order for the UT699 to begin fetching code from PROM.

During normal operation, the indicated bus control signals will go to a valid-inactive state, and the bi-directs will go to a high-Z

4.1.4 Programming Pins GPIO[2:0]

Data on pins GPIO[2:0] are latched on the rising edge of reset. The states of these pins determine the data width of the PROM area,

and enable EDAC for the PROM area. Chapter 3 of the User’s Manual describes the value of these inputs to achieve the required

operation.

In order for the state of GPIO[2:0] to be properly latched, it is recommended to place pull-up or pull-down resistors on these pins to

ensure that the setup and hold timing is met. The states of these pins should be statically set prior to the rising edge of RESET.

4.2 Output Timing Characteristics for Memory Interface, ERROR, and WDOG

Notes:

1. All outputs are measured using the load conditions shown in Figure 15.

2. High-Z defined as +/-300mV change from steady state.

Symbol

Description

Min

Max

Units

(ADDR[27:0], WRITE, OE, IOS, ROMS[1:0], RWE [3:0], RAMOE

[4:0], RAMS[4:0], READ, SDRAS, SDCAS, SDWE, SDCS[1:0], and

SDDQM[3:0])

28

ns

(DATA[31:0] and CB[7:0])

28

ns

(DATA[31:0] and CB[7:0])

28

ns

(ERROR and WDOG)

29

ns

(DATA [31:0] and CB[7:0])

2.5

-

ns

Skew from first memory output signal transition to last memory output

signal transition

-2

ns