ADA8282

Data Sheet

Rev. 0 | Page 12 of 21

PROGRAMMABLE GAIN RANGE

The ADA8282 has a programmable gain to allow adjusting of

the output amplitudes of signals to accommodate a variety of

applications. The gain of the ADA8282 is programmable in 6 dB

increments from 18 dB to 36 dB. The gain is controlled using

Register 0x15. The same register controls all four channels, but

each channel can be independently controlled by utilizing the

appropriate bits in the register. Channel A is controlled with the

two LSBs of Register 0x15 (Bits[1:0]), Channel B uses Bits[3:2],

Channel C uses Bits[5:4], and Channel D uses the two MSBs,

Bits[7:6].

The gain setting and gains are listed in Table 7.

Table 7. Gain Settings

Register 0x15 Setting

Gain (dB)

Gain (V/V)

b’00

18

7.9

b’01

24

15.9

b’10

30

31.6

b’11

36

63.1

OUTPUT SWING VARIATION WITH GAIN

The ADA8282 gain is implemented using two internal gain stages.

The first stage is an LNA with a gain of 24 dB, and the second

stage is a PGA with a gain that varies from −6 dB to +12 dB. The

output of the LNA has a fixed output swing range, and is the

limiting factor when the channel gain is 18 dB. Because of the

limitations of the LNA swing range, the ADA8282 has an output

swing that is dependent on gain, as shown in Table 8.

Table 8. Output Swing at Various Gains

Gain (dB)

Output Swing (V p-p)

18

3.1

24

6.3

30

6.3

36

6.3

OFFSET VOLTAGE ADJUSTMENTS

Register 0x10 through Register 0x13 adjust the dc offset voltage

of each channel. The default value of 0x20 is intended to be the

setting for the offset closest to 0 V, but adjustments can be made

as required by the application.

The default setting (0x20) applies a zero offset, 0x00 applies the

maximum negative offset, and 0x3F applies the maximum

positive offset.

The range and resolution of the LNA_OFFSETx adjustments

are dependent on the LNA bias mode as described in Table 9.

Table 9. Offset Voltage Adjustments

LNA_BIAS_SEL

Setting

Referred to Input (RTI)

Offset Resolution (μV)

RTI Offset

Range (mV)

b’00

113

±4

b’01

186

±6

b’10

250

±8

b’11

440

±14

VIO Pin

The VIO pin sets the voltage levels used by the SPI interface. If

the VIO pin is tied to the 3.3 V supply, the SPI port functions

on 3.3 V logic.

SINGLE-ENDED OR DIFFERENTIAL INPUT

The ADA8282 operates with either a differential or single-ended

signal source. The maximum input voltage swing is the same in

either configuration. When using a single-ended signal source,

connect the unused input to ground with a capacitor. Matching

the ac coupling capacitor to the ac grounding capacitor

optimizes CMRR performance.

SHORT-CIRCUIT CURRENTS

The ADA8282 typically has a 205 mA short-circuit current per

output pin. The thermal implications of this current during

unintended shorting of these outputs must be taken into account

when designing boards with this device.

SPI INTERFACE

The ADA8282 SPI interface uses a 4-wire interface to deliver a

16-bit instruction header, followed by 8 bits of data. The first bit

is a read/write bit. W1 and W0 determine how many bytes are

transferred, and must both be zeros for the ADA8282 to write to a

single register. Then, a 13-bit address and an 8-bit data byte follow.

The SPI port operates at SCLK frequencies of up to 10 MHz.

For additional SPI timing information, see the AN-877

Application Note.

A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

A12

W0

W1

R/W

CS

SCLK

SDI

DON’T CARE

DON’T CARE

DON’T CARE

DON’T CARE

16-BIT INSTRUCTION HEADER

MSB-FIRST 16-BIT INSTRUCTION

REGISTER (N) DATA

Figure 26. Serial Instruction Details