Data Sheet

ADA8282

Rev. 0 | Page 17 of 21

REGISTER MAP

REGISTER SUMMARY

Table 12. Register Summary

Reg. Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset RW

0x00 INTF_CONFA

[7:0]

INTF_CONFA2

LSBFIRST1

INTF_CONFA1

LSBFIRST0

INTF_CONFA0

0x00

RW

0x01 SOFT_RESET

[7:0]

Unused

SOFT_RESET

0x00

R

0x04 CHIP_ID1

[7:0]

CHIP_IDLOW

0x82

R

0x05 CHIP_ID2

[7:0]

CHIP_IDHI

0x82

R

0x06 Revision

[7:0]

Revision

0x00

R

0x10 LNA_OFFSET0 [7:0]

Unused

LNA_OFFSET0

0x20

RW

0x11 LNA_OFFSET1 [7:0]

Unused

LNA_OFFSET1

0x20

RW

0x12 LNA_OFFSET2 [7:0]

Unused

LNA_OFFSET2

0x20

RW

0x13 LNA_OFFSET3 [7:0]

Unused

LNA_OFFSET3

0x20

RW

0x14 BIAS_SEL

[7:0]

Unused

PGA_BIAS_SEL

LNA_BIAS_SEL

0x0A RW

0x15 PGA_GAIN

[7:0]

PGA_GAIN3

PGA_GAIN2

PGA_GAIN1

PGA_GAIN0

0x00

RW

0x17 EN_CHAN

[7:0]

Unused

EN_

CHANNEL3

EN_

CHANNEL2

EN_

CHANNEL1

EN_

CHANNEL0

0x00

RW

0x18 EN_BIAS_GEN [7:0]

Unused

EN_BIAS_GEN 0x00

RW

0x1D SPAREWR0

[7:0]

Unused

GPIO_WRITE GPIO_WR_

MODE

0x00

RW

0x1E SPARERD0

[7:0]

Unused

GPIO_READ

0x00

R

REGISTER DETAILS

Register 0x00: Interface Configuration Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTF_CONFA2

LSBFIRST1

INTF_CONFA1

LSBFIRST0

INTF_CONFA0

The INTF_CONFA configuration register is symmetric, as it is the first register written and sets the data direction (LSB first or MSB first).

Table 13. INTF_CONFA Configuration Register Bit Descriptions

Bits

Bit Name

Description

Reset

Access

[7:0]

INTF_CONFA2

INTF_CONFA2 must remain b’00.

0x00

RW

5

LSBFIRST1

LSBFIRST1 must be set to b’1 for LSB first operation and to b’0 for MSB first operation.

0x00

RW

[4:3]

INTF_CONFA1

INTF_CONFA1 must remain b’00.

0x00

RW

2

LSBFIRST0

LSBFIRST0 must be set to b’1 for LSB first operation and to b’0 for MSB first operation.

0x00

RW

[1:0]

INTF_CONFA0

INTF_CONFA0 must remain b’00.

0x00

RW

Register 0x01: Soft Reset Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Unused

SOFT_RESET

Table 14. SOFT_RESET Configuration Register Bit Descriptions

Bits

Bit Name

Description

Reset

Access

0

SOFT_RESET

The SOFT_RESET bit resets all registers to their default values when SOFT_RESET is set to b’1.

0x00

RW

Register 0x04: Chip ID Low Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CHIP_IDLOW

Table 15. CHIP_IDLOW Configuration Register Bit Descriptions

Bits

Bit Name

Description

Reset

Access

[7:0]

CHIP_IDLOW

The CHIP_ID1 and CHIP_ID2 registers identify the ADA8282.

0x82

R