Data Sheet

ADA8282

Rev. 0 | Page 19 of 21

Table 20. LNA_OFFSET2 Configuration Register Bit Descriptions

Bits

Bit Name

Description

Reset

Access

[5:0]

LNA_OFFSET2

LNA_OFFSET0 controls the offset of Channel C. The default setting (0x20) applies the minimum

offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset.

0x20

RW

The resolution of the offset varies with the LNA bias mode as follows:

LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range.

LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range.

LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range.

LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range.

Register 0x13: LNA Offset 3 Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Unused

LNA_OFFSET3

Table 21. LNA_OFFSET3 Configuration Register Bit Descriptions

Bits

Bit Name

Description

Reset

Access

[5:0]

LNA_OFFSET3

LNA_OFFSET0 controls the offset of Channel D. The default setting (0x20) applies the minimum

offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset.

0x20

RW

The resolution of the offset varies with the LNA bias mode as follows:

LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range.

LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range.

LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range.

LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range.

Register 0x14: PGA Bias Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Unused

PGA_BIAS_SEL

LNA_BIAS_SEL

The PGA bias select register allows the user to trade off power and performance (for example, bandwidth and noise).

Table 22. BIAS_SEL Configuration Register Bit Descriptions

Bits

Bit Name

Description

Reset

Access

[3:2]

PGA_BIAS_SEL

Set PGA_BIAS_SEL to b’00 for the minimum PGA bias and to b’11 for the maximum PGA bias.

0x00

RW

[1:0]

LNA_BIAS_SEL

Set LNA_BIAS_SEL to b’00 for the minimum LNA bias and to b’11 for the maximum LNA bias.

0x00

RW

Register 0x15: PGA Gain Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PGA_GAIN3

PGA_GAIN2

PGA_GAIN1

PGA_GAIN0

The PGA gain register allows independent gain settings for each channel.

Table 23. PGA_GAIN Configuration Register Bit Descriptions

Bits

Bit Name

Description

Reset

Access

[7:6]

PGA_GAIN3

Set PGA_GAIN3 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to

b’11 for 36 dB gain for Channel D

0x00

RW

[5:4]

PGA_GAIN2

Set PGA_GAIN2 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to

b’11 for 36 dB gain for Channel C

0x00

RW

[3:2]

PGA_GAIN1

Set PGA_GAIN1 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to

b’11 for 36 dB gain for Channel B

0x00

RW

[1:0]

PGA_GAIN0

Set PGA_GAIN0 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to

b’11 for 36 dB gain for Channel A

0x00

RW