ADA8282

Data Sheet

Rev. 0 | Page 20 of 21

Register 0x17: Enable Channel Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Unused

EN_CHANNEL3

EN_CHANNEL2

EN_CHANNEL1

EN_CHANNEL0

The enable channel register allows individual channels to be enabled or disabled. The default mode for the channel is disabled. Write 0x0F

to the EN_CHAN register to enable all channels.

When a channel is disabled but the bias generator is still enabled, the channel’s current consumption is <100 μA. When a channel is

disabled, its output pins are high-Z. The enable channel register resets at AVDD power-on to 0x00 to avoid inrush current for fast supply

ramps.

Table 24. EN_CHAN Register Bit Descriptions

Bits

Bit Name

Description

Reset

Access

3

EN_CHANNEL3

Set to b’1 to enable Channel D, and set to b’0 to disable Channel D

0x00

RW

2

EN_CHANNEL2

Set to b’1 to enable Channel C, and set to b’0 to disable Channel C

0x00

RW

1

EN_CHANNEL1

Set to b’1 to enable Channel B, and set to b’0 to disable Channel B

0x00

RW

0

EN_CHANNEL0

Set to b’1 to enable Channel A, and set to b’0 to disable Channel A

0x00

RW

Register 0x18: Enable Bias Generator Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Unused

EN_BIAS_GEN

When any channel is enabled, the bias generator is automatically enabled. The EN_BIAS_GEN register controls whether the bias

generator stays active, even when all channels are disabled. Leaving the bias generator active decreases the enable time of the device.

Table 25. EN_BIAS_GEN Register Bit Descriptions

Bits

Bit Name

Description

Reset

Access

0

EN_BIAS_GEN

Setting EN_BIAS_GEN to 1 keeps the bias generator active, providing a faster enable time (~2 μs).

0x00

RW

Register 0x1D: GPIO Write Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Unused

GPIO_WRITE

GPIO_WR_MODE

The GPIO_WR_MODE bit reconfigures the SDO pin to a general-purpose input/output (GPIO) port that can be written by the

GPIO_WRITE register or read by the GPIO_READ register.

Table 26. SPAREWR0 Configuration Register Bit Descriptions

Bits

Bit Name

Description

Reset

Access

1

GPIO_WRITE

Data bit is put onto the SDO pin when GPIO write mode is active.

0x00

RW

0

GPIO_WR_MODE

Write b’1 to this register to activate GPIO write mode.

0x00

RW

Register 0x1E: GPIO Read Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Unused

GPIO_READ

Table 27. SPARERD0 Configuration Register Bit Descriptions

Bits

Bit Name

Description

Reset

Access

0

GPIO_READ

This register reflects the logic level placed on SDO when a b’0 is written to GPIO_WR_MODE.

0x00

R