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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SWCS049D 数据表(PDF) 42 Page - Texas Instruments |
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SWCS049D 数据表(HTML) 42 Page - Texas Instruments |
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42 / 119 page  1.2 V EN1 PFM (pulse skipping) mode SW1 VDD1/VFB1 0.8 V PFM (pulse skipping) mode PFM (pulse skipping) mode PWM mode PWM mode t dDVSEN t dDVSENL t dDVSEN TSTEP[2:0]=001 TSTEP[2:0]=011 t dDVSENL SWCS049-011 42 TPS659110, TPS659112, TPS659113 TPS659114, TPS659118, TPS6591133 SWCS049Q – JUNE 2010 – REVISED MARCH 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133 Specifications Copyright © 2010–2016, Texas Instruments Incorporated 5.23.2.5 VDD1, VDD2 Voltage Control Through EN1 and EN2 Signals NOTE: Register setting: VDD1_EN1 = 1, SEL[6:0] = hex13 in VDD1_SR_REG Figure 5-8. VDD1 Supply Voltage Control Through EN1 Table 5-6. VDD1 Supply Voltage Control Through EN1 Timing Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tdDVSEN EN1 (or EN2) edge to VDD1 (or VDD2) voltage change delay 2 × tCK32k = 62 µs tdDVSENL VDD1 (or VDD2) voltage settling delay TSTEP[2:0] = 001 32 µs TSTEP[2:0] = 011 (default) 0.4 / 7.5 = 53 TSTEP[2:0] = 111 160 |
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