SWCS049D datasheet(46/119 Pages) TI1

46 / 119 page

TPS659110, TPS659112, TPS659113

TPS659114, TPS659118, TPS6591133

SWCS049Q – JUNE 2010 – REVISED MARCH 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133

Detailed Description

The SLEEP state can be controlled by programming DEV_SLP bit and keeping the SLEEP signal in the

active polarity state, or it can be controlled through the SLEEP signal setting the DEV_SLP bit to 1 after

device turnon.

6.3.1.4

Device Reset Scenarios

The device has three reset scenarios:

•

Full reset: All digital logic of device is reset.

–

Caused by POR (power on reset) when VCC7 < VBNPR and BB < VBNPR

•

General reset: No impact on the RTC, backup registers, or interrupt status.

–

Caused by PWON_LP_RST bit set high

–

Or DEV_OFF_RST bit set high

–

Or HDRST input set high

•

Turnoff: Power reinitialization in off/backup mode.

A mapping of digital registers to these reset scenarios is described in Table 6-6.

6.3.2

BOOT Configuration, Switch-ON, and Switch-OFF Sequences

The power sequence is the automated switch-on of the devices resources when an OFF-to-ACTIVE

transition occurs. The power-on sequence has 15 sequential time slots to which resources (DC-DC

converters, LDOs, 32-kHz clock, GPIO0, GPIO2, GPIO6, GPIO7) can be assigned. The time slot length

can be selected to be 0.5 ms or 2 ms. If a resource is not assigned to any time slot, it will be in off mode

after the power-on sequence and the voltage level can be changed through the register SEL bits before

enabling the resource.

Power off disables all power resources at the same time by default. By setting the PWR_OFF_SEQ

control bit to 1, power off will follow the power-up sequence in reverse order (the first resource to be

powered on will be last to power off).

The values of VDD1, VDD2, and VDDCtrl set in the boot sequence can be selected from 16 steps. For the

whole range, 100-mV steps are available: 0.6/0.7...1.4/1.5 V. From 0.8 to 1.4 V, additional values with

50-mV step resolution can be set: 0.85/1.05...1.35 V.

For LDO1, LDO2, and LDO4 all levels from 1.0 to 3.3 V are selectable in the boot sequence with 50-mV

steps. For other LDOs, the level is selectable with 100-mV steps, from 1.0 to 3.3 V.

The device supports three boot configurations, which define the power sequence and several device

control bits. The boot configuration is selectable by the device BOOT1 pin.

BOOT1

Boot Configuration

Floating

Test boot mode

Fixed boot mode

EEPROM boot mode

The BOOT1 input pad is disabled after the boot mode is read at power up, to save power.

Table 6-2 and Table 6-3 describe the power sequence and general control bits defined in the boot

sequence, respectively.

Fixed boot mode is the same in all devices, while EEPROM boot mode is different in each device. For

EEPROM boot mode description refer to the user's guide for the selected device.

SWCS049D 数据表(PDF) 46 Page - Texas Instruments

SWCS049D 数据表(HTML) 46 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载