SWCS049D datasheet(51/119 Pages) TI1

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TPS659110, TPS659112, TPS659113

TPS659114, TPS659118, TPS6591133

www.ti.com

SWCS049Q – JUNE 2010 – REVISED MARCH 2016

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Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133

Detailed Description

The EN2 and EN1 signals can be used to set the output voltage of VDD1 and VDD2 SMPS from a roof to

floor

value,

preprogrammed

the

VDD1_OP_REG,

VDD2_OP_REG

and

VDD1_SR_REG,

VDD2_SR_REG registers.

When a supply is controlled through the EN1 or EN2 signals, its state is no longer driven by the device

SLEEP state.

6.3.3.9

GPIO0 to GPIO8

GPIO0, GPIO2, GPIO6, and GPIO7 can be programmed to be part of the power-up sequence and used

as enable signals for external resources.

GPIO0 is a configurable I/O in the VCC7 domain. By default, its output is push-pull, driving low. GPIO0

can also be configured as an open-drain output with external pullup.

GPIO1 through GPIO8 are configurable open-drain digital I/Os in the VRTC domain. GPIO directivity,

debouncing delay, and internal pullup can be programmed. By default, all are inputs with weak internal

pulldown; as open-drain output an external pullup is required.

GPIO0, GPIO1, and GPIO3 through GPIO5 can be used to turn on the device if the corresponding

interrupt is not masked. When configured as an input, GPIO2 cannot be used to turn on the device, even if

its associated interrupt is not masked. The GPIO interrupt is level sensitive. When an interrupt is detected,

before clearing the interrupt, it should first be disabled by masking it.

GPIO1 and GPIO3, which have current sink capability of 10 mA, can also be used to drive LEDs

connected to a 5-V supply.

GPIO2 can be used for synchronizing DC-DC converters to an external clock. Programming DCDCCKEXT

= 1, VDD1, VDD2, and VIO DCDC switching can be synchronized using a 3-MHz clock set though the

GPIO2 pin. VDD1 and VDD2 will be in-phase and VIO will be phase shifted by 180 degrees.

It is recommended not to connect noisy switching signals to GPIO4 and GPIO5.

6.3.3.10 HDRST Input

HDRST is a cold reset input for the PMIC. High level at input forces the TPS65911x into off mode, causing

a general reset of device to the default settings. The default state is defined by the register reset state and

boot configuration. HDRST high level keeps the device in off mode. When reset is released and HDRST

input goes low, the device automatically transitions to active mode. The device is kept in active mode for

the period tDONIT1, after which another power-on enable reason is needed to maintain the device on.

The HDRST input is in the VRTC domain and has a weak internal pulldown, which is active by default.

6.3.3.11 PWRDN

The PWRDN input is a reset input with selectable polarity (PWRDN_POL). High(low) level at input forces

the TPS65911x device into off mode, causing a power-off reset. Off mode is maintained until PWRDN is

released and a start-up reason (for example, PWRON button press or DEV_ON = 1) is detected. An

interrupt is generated to indicate the cause for shutdown. The PWRDN input is in the VRTC domain but

can tolerate a 5-V input.

SWCS049D 数据表(PDF) 51 Page - Texas Instruments

SWCS049D 数据表(HTML) 51 Page - Texas Instruments

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